In the continuing effort to improve performance of transistors and integrated circuits (ICs) in which they are used, semiconductor device designers strive to increase the drive current of the devices to increase switching speeds and overall performance. One aspect of this effort includes incorporating stress into the channel region of the device.
However, as overall device size has decreased, problems associated with the manufacturing processes used to accomplish increased drive current have arisen. For example, in typical processes, a relatively thick (800 angstroms to 1000 angstroms) stress inducing layer is deposited over the gate electrode structures. A thick layer is used because more stress can be incorporated into the channel by utilizing a thick layer of material, which allows for a greater increase in drive current. However, when these thick layers are annealed, they can often provide a torque stress on the gate electrode, thereby causing a portion of the gate electrode to crack and break off. This, of course, is unacceptable as it increases defects across a semiconductor wafer and consequently decreases yields.
Accordingly, what is needed is a method for increasing drive current by stress induction while minimizing damage to the gate electrodes.